1. Field of the Invention
The present invention generally relates to a program checking method, a program checking apparatus, and a computer-readable recording medium for recording thereon a target program checking program. More specifically, the present invention is directed to such program checking method/apparatus capable of checking a target program while reducing total tracing interrupt time, which should be executed by a central processing unit (CPU) for constituting a target system such as a facsimile machine under development and an image processing apparatus under development. Also, the present invention is directed to a computer-readable recording medium for recording thereon such a target program to be executed by this CPU.
2. Description of the Related Art
There is a rare case that a target program installed in a target system is operable under normal condition since this target program has been accomplished. Therefore, usually, a program checking apparatus executes this target program so as to trace contents of this target program step by step, for instance, how the respective instructions (commands) for constituting the target program are executed; how the contents of registers are changed after the respective instructions are executed, and/or how the contents of addresses within a main storage apparatus are changed. Then, the information related to these traced contents (historical information) is acquired to be stored into the external storage apparatus. Thereafter, this target program containing program bugs can be corrected based upon the acquired historical information.
Conventionally, an address bus and a data bus, which are connected to a CPU, are connected with a target program checking apparatus so as to acquire desirable historical information at preset timing. Then, the acquired historical information is stored into a storage apparatus contained in this target program checking apparatus. Very recently, operation capabilities of CPUs are increased, and operation clock frequencies thereof are also increased up to several 100 MHz. When connectors and/or probes of target program checking apparatus are electrically connected to address buses and/or data bus operable in such high frequencies, unwanted stray capacitances are additionally provided with these high-speed address buses/data buses. Therefore, signal waveforms of address signal and/or data signals would be deformed, so that the target system could not be operated under normal condition.
Furthermore, when a cache memory circuit is built in a CPU, an external storage unit is not sometimes accessed. Thus, even when an external address bus and an external data bus are traced, there is such a risk that steps processed by the CPU cannot be completely traced. Under such a reason, a trace means is conventionally provided within a CPU chip, and necessary historical information is outputted via a trace terminal outside the CPU chip.
In general, when a target program checking apparatus is employed, a storage capacity for tracing operation may be increased as large as possible, as compared with a CPU chip having a trace data memory. Moreover, when a high speed memory is employed, a large amount of historical information may be acquired. However, when such a trace information storage unit is provided inside a CPU chip and a storage capacity thereof is increased, cost of this CPU chip is increased. Therefore, this measure does not constitute merits. On the other hand, when a total number of tracing terminals is increased so as to acquire data in high speed, a dimension of an IC chip package is increased, result in one of demerits.
As a consequence, it is practically difficult to determine how such historical information can be acquired in a high efficiency with using a limited storage capacitance for storing historical information, and a limited number of tracing terminals.
One typical conventional program checking apparatus has been proposed. That is, as indicated in FIG. 11, this target program checking apparatus is mainly arranged by a target memory unit 1, a CPU chip 2, and an external storage apparatus 3. The target memory unit 1 is a memory functioning as a main storage apparatus of a target system, and is arranged by a target program storage unit 1a for storing thereinto a target program to be checked by a CPU, and a data storage unit 1b for storing thereinto data used while this target program is executed.
The CPU chip 2 is mainly arranged by a target register unit 4, a CPU 5, a trace means 6, and a trace buffer 7. The target register unit 4 is realized by simulating a register used by the CPU chip 2. This target register unit 4 is constituted by a plurality of registers. The CPU 5 controls various structural elements employed in the conventional program checking apparatus, and also sequentially executes the target program. The trace means 6 traces one by one the execution sequence of the respective instructions for constituting the target program, and the change states in the storage contents of the target register unit 4 after the respective instructions are executed so as to acquire historical information related to these traced results. Thereafter, the trace means 6 stores the historical information into the external storage apparatus 3. As the historical information, for instance, there are an address of a destination on the target program storage unit 1a as a condition branch instruction; an address of a jump destination on the target program storage unit 1a as a jump instruction; and an address of data loaded to the target register unit 4 on the data storage unit 1b as a data load instruction. The trace buffer 7 owns a preselected storage capacity. The historical information is sequentially stored into this trace buffer 7 in a cyclic manner. The external storage apparatus 3 is constituted by such a storage medium having a large storage capacity, for instance, a semiconductor memory such as a RAM, a floppy disk (FD), and a hard disk (HD). The historical information is stored into this external storage apparatus 3.
Next, a description is made of the operations of the above-described conventional program checking apparatus. The CPU 5 sequentially reads the respective commands/instructions for constituting this target program from the target program storage unit 1a, and interprets any of the instructions/commands. For example, the respective commands are executed in such a manner that the data stored in the data storage unit 1b is loaded on the target register unit 4. As a result, the trace means 6 traces in the unit of one step the execution sequence of the respective instructions, and also the state changes in the storage contents of the target register unit 4. Then, this trace means 6 acquires the historical information related to these traced events, and sequentially stores the acquired historical information into the trace the trace buffer 7.
When the trace means 6 repeatedly performs the above-described process operations and therefore, the trace buffer 7 will overflow, the trace means 6 requests the CPU 5 to once stop the program processing operation under execution, during which all of the historical information stored in the trace buffer 7 is stored into the external storage apparatus 3. Thereafter, when the transfer buffer 7 becomes empty, the trace operation is restarted.
In the above-described conventional program checking apparatus, since the operation of this CPU 5 is stopped every time the trace buffer 7 is brought into the overflow operation, this program checking apparatus cannot be applied to such a target program checking operation that the program checking operation should be carried out in real time. For instance, in the case that a program developed for controlling an engine of an automobile is checked, such information for indicating how degree a car driver pushes an acceleration pedal, or what revolution number of this engine is counted, or what temperature becomes is entered into the CPU. This CPU controls a fuel supply amount and fuel supply timing based on this information. A program developing engineer actuates the engine so as to obtain an optimum fuel supply amount by changing various parameters which are set to the CPU. At this time, this program developing engineer progresses this development by confirming how the program is processed within the CPU, and which parameters are used.
When the historical information is acquired by the conventional program checking apparatus in such a manner that the program processing operation is once stopped, the engine is also stopped, so that the historical information under actual use condition could not be acquired.
To avoid this problem, one solution method has been described in Japanese Patent Application Laid-open No. Hei-5-181713. That is, the historical information may be acquired only when the program is ended under abnormal condition. However, this conventional acquiring method cannot acquire the contents of the resisters operated under normal operation, so that the program developing engineer could not grasp how the CPU is operated with parameters.